A memory device is generally provided as an internal semiconductor integrated circuit in a computer or other electronic devices. In the memory device, there are various different kinds of memories including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) and flash memory. In particular, the flash memory device was developed and has become popular for supplying a non-volatile memory for a wide range of electronic applications. For the flash memory device, high memory density (degree of integration), high reliability, and low power consumption should be generally considered.
A semiconductor chip has been developed in view of degree of integration according to Moore's law since a bipolar transistor was developed at Bell Labs in 1947. This development has been ongoing in accordance with the continuous development of a photoetching process. However, recently, according to the International Technology Roadmap for Semiconductor (ITRS), it is known that a process technology of 30 nm or less has many problems in being implemented due to limitation of the photoetching technology. Accordingly, a technology for fabricating various nanopatterns is being developed based on a new principle, and among these research fields, research into a molecularly assembled nanostructure has received attention around the world.
As described above, in order to increase memory density in the semiconductor devices such as a flash memory, and the like, an attempt to increase degree of integration of the semiconductor device has continued. Area occupied by each unit cell in a plane is decreased, and in accordance with the decrease in unit cell area, a design rule of small nanoscale critical dimension (CD) at several to several tens of nm level has been applied, and thus, the new technology for fabricating fine patterns such as fine contact hole patterns having nanoscale opening size or fine line patterns having a nanoscale width has been demanded.
When formation of fine patterns for manufacturing a semiconductor device depends on only photolithography in a top-down scheme, there is a limitation in improving resolving power due to a wavelength limit of light source and resolution limit of an optical system, and the like. A method of forming a fine structure in a bottom-up scheme using self-assembly phenomenon of molecules was attempted as one effort for overcoming a resolution limit in the photolithography technology and developing the next generation fine processing technology.
The most representative polymer material forming the molecularly assembled nanostructure is a block copolymer (BCP) having a molecular structure in which chemically different domain blocks are covalently linked to each other. As a result, the block copolymer may form various nanostructures such as sphere, cylinder, lamella, and the like, having several to several tens of nano levels of uniformity, and have advantages of thermal stability, and an ability to design size and physical properties of the nanostructure in a synthesis step. In addition, the nanostructure may be rapidly implemented in a large area by a parallel process, and after forming inorganic and organic nanostructure thin films, a block copolymer template is easily removed, such that intensive research as a technology for fabricating nanopatterns for manufacturing various second generation devices such as a nanowire, quantum dots, magnetic storage medium, non-volatile memory, and the like, in IT, BT, and ET fields has been conducted.
Among them, polystyrene-block-polymethylmethacrylate (PS-B-PMMA) may be easily synthesized, and may form a vertical lamella or a cylinder nano structure at a high ratio through vacuum annealing which is easily capable of being implemented at fabrication facility. Further, pattern transcription after performing selective etching of PMMA nanodomain is easily performed. Nevertheless, in PS-b-PMMA having significantly low χ (segment interaction) value, patterns of 12 nm or less may not be formed, which is a problem in 10 nm scale pattern currently required in a semiconductor industry.